1. Field of the Invention
The present invention relates to a semiconductor testing method and a semiconductor tester for testing a semiconductor or conducting a failure analysis with the function of a scanning electron microscope (SEM).
2. Background Art
As failure analyses conducted on semiconductors having basic patterns regularly disposed in a repeated manner, failure analyses are conducted on semiconductors through images obtained by scanning electron microscopes (SEMs) and focused ion beams (FIBs).
In recent years, semiconductor miniaturization has proceeded to 45/65 nm, which is a level higher than the accuracies of stopping stages. Thus it has become difficult to locate a failure even with high-powered microscopes. Further, some failures cannot be recognized at all from the appearances even through observation using SEM images. To be specific, such failures cannot be recognized until probes are brought into contact with the points of failures to measure device characteristics.
In this case, it is necessary to accurately count the positions of failures among completely identical basic patterns disposed in a repeated manner. This is because it is completely meaningless to measure the electrical characteristics of a cell adjacent to the position of a failure.
Particularly, examples of a method of accurately counting failed cells having repeatedly disposed basic patterns include, as described in JP Patent Publication (Kokai) No. 2000-251824A, a pattern matching method, a method of reaching a location of measurement from absolute distance information about a stage, and a method of counting failed cells while moving a stage.
Since pattern recognition is used in the pattern matching method of the conventional art, it is necessary to divide, before recognition, a distance to a destination into units enabling image recognition. Further, since it is desired to keep the movement of a stage as long as possible, the maximum distance enabling image recognition is equivalent to one screen. Since a correction is made for each screen, when a specific cell A in a screen is moved with a stage substantially by one screen, the cell A may be placed out of a specific region for pattern matching due to semiconductor miniaturization. Further, the initial speed and stopping speed of the stage become unstable during the movement. Moreover, the stage is stopped for each screen, causing a drawback of a low speed in view of performance.
In other words, due to semiconductor miniaturization, the accuracy of stopping the stage may cause an error equal to or larger than a spacing between cells relative to the movement of the stage for each screen, so that the cells may be erroneously detected. Although it is convenient to count cells both in rows and columns at the same time, the stage simultaneously moves in both directions and thus an erroneously recognized adjacent cell cannot be visually confirmed. Therefore, such counting is hard to realize.
Further, in the method of reaching a location of measurement based on absolute distance information about a stage according to the conventional art, the position of a failure is calculated from a design drawing by using a CADNavi system and the like, and then the stage is moved. In this method, the accuracy of stopping the stage is larger than the spacing between cells and thus a failure cannot be accurately located. As a matter of course, it is preferable that the stage can be stopped with high accuracy and can be correctly moved. In either case, a failure has to be accurately located.
Further, in the method of counting cells while moving a stage according to the conventional art, several hundreds of thousands of counts are simply necessary. Such counting is practically impossible.
An object of the present invention is to realize a semiconductor testing method and a semiconductor tester which can quickly and accurately count semiconductor cells.